1. Field of the Invention
The field of the invention is data processing, or, more specifically, methods, apparatus, and products for broadcasting collective operation contributions throughout a parallel computer.
2. Description of Related Art
The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely complicated devices. Today's computers are much more sophisticated than early systems such as the EDVAC. Computer systems typically include a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input/output devices, and so on. As advances in semiconductor processing and computer architecture push the performance of the computer higher and higher, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in computer systems today that are much more powerful than just a few years ago.
Parallel computing is an area of computer technology that has experienced advances. Parallel computing is the simultaneous execution of the same task (split up and specially adapted) on multiple processors in order to obtain results faster. Parallel computing is based on the fact that the process of solving a problem usually can be divided into smaller tasks, which may be carried out simultaneously with some coordination.
Parallel computers execute parallel algorithms. A parallel algorithm can be split up to be executed a piece at a time on many different processing devices, and then put back together again at the end to get a data processing result. Some algorithms are easy to divide up into pieces. Splitting up the job of checking all of the numbers from one to a hundred thousand to see which are primes could be done, for example, by assigning a subset of the numbers to each available processor, and then putting the list of positive results back together. In this specification, the multiple processing devices that execute the individual pieces of a parallel program are referred to as ‘compute nodes.’ A parallel computer is composed of compute nodes and other processing nodes as well, including, for example, input/output (‘I/O’) nodes, and service nodes.
Parallel algorithms are valuable because it is faster to perform some kinds of large computing tasks via a parallel algorithm than it is via a serial (non-parallel) algorithm, because of the way modern processors work. It is far more difficult to construct a computer with a single fast processor than one with many slow processors with the same throughput. There are also certain theoretical limits to the potential speed of serial processors. On the other hand, every parallel algorithm has a serial part and so parallel algorithms have a saturation point. After that point adding more processors does not yield any more throughput but only increases the overhead and cost.
Parallel algorithms are designed also to optimize one more resource the data communications requirements among the nodes of a parallel computer. There are two ways parallel processors communicate, shared memory or message passing. Shared memory processing needs additional locking for the data and imposes the overhead of additional processor and bus cycles and also serializes some portion of the algorithm.
Message passing processing uses high-speed data communications networks and message buffers, but this communication adds transfer overhead on the data communications networks as well as additional memory need for message buffers and latency in the data communications among nodes. Designs of parallel computers use specially designed data communications links so that the communication overhead will be small but it is the parallel algorithm that decides the volume of the traffic.
Many data communications network architectures are used for message passing among nodes in parallel computers. Compute nodes may be organized in a network as a ‘torus’ or ‘mesh,’ for example. Also, compute nodes may be organized in a network as a tree. A torus network connects the nodes in a three-dimensional mesh with wrap around links. Every node is connected to its six neighbors through this torus network, and each node is addressed by its x,y,z coordinate in the mesh. In a tree network, the nodes typically are connected into a binary tree: each node has a parent, and two children (although some nodes may only have zero children or one child, depending on the hardware configuration). In computers that use a torus and a tree network, the two networks typically are implemented independently of one another, with separate routing circuits, separate physical links, and separate message buffers.
A torus network generally supports point-to-point communications. A tree network, however, typically only supports communications where data from one compute node migrates through tiers of the tree network to a root compute node or where data is multicast from the root to all of the other compute nodes in the tree network. In such a manner, the tree network lends itself to collective operations such as, for example, reduction operations or broadcast operations. In the current art, however, the tree network does not lend itself to and is typically inefficient for point-to-point operations. Although in general the torus network and the tree network are each optimized for certain communications patterns, those communications patterns may be supported by either network.
One of the most common communications patterns utilized in a parallel computer is an all-to-all communication pattern. An all-to-all communication pattern is often used in sorting, matrix multiplication, and matrix transposition application. In this communication pattern, each compute node sends a distinct message to each other compute node in the parallel computer—resulting in a communication pattern that is extremely network intensive.
Because of the importance of the all-to-all communications pattern and because of the network intensive nature of the pattern, many algorithms exist to optimize the all-to-all communications pattern on a variety of computing platforms. The drawback, however, is that such algorithms are designed for parallel computers having single-processor compute nodes that exclusively utilize a distributed-memory architecture, and therefore these algorithms typically do not operate efficiently in parallel computers with multi-core compute nodes or nodes that utilize shared memory. In such parallel computers, the inefficiencies often result from bandwidth constraints as multiple processors on a compute node compete for use of the same network links to pass their all-to-all contributions to the other compute nodes through the network.